压缩包内容如下：
A[31:3]# Input/Output A[31:3]# (Address) define a 232-byte physical memory address space. In subphase1 of the address phase, these pins transmit the address of a transaction.In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on Intel® Pentium® M Processor FSB. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted.
A20M# Input If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode.A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.
ADS#Input/Output ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.
ADSTB[1:0]# Input/Output Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Signals/ Associated Strobe
REQ[4:0]#, A[16:3]#/ ADSTB[0]#； A[31:17]#/ ADSTB[1]#。
BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
BNR#Input/Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.
BPM[2:0]#BPM[3] In/out, Out BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Intel® Pentium® M FSB agents.This includes debug or performance monitoring tools.
BPRI#Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#
BR0#Input/Output BR0# is used by the processor to request the bus. The arbitration is done between Intel® Pentium® M (Symmetric Agent) and Intel® 915PM/GM and Intel® 915GMS Express chipset GMCH-M (High Priority Agent).
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BSEL[1:0] Output BSEL[1:0] (Bus Select) are used to select the processor input clock frequency.Table 3-2 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Pentium M Processor operates at a 533-MHz front side bus frequency (133 MHz BCLK).
COMP[3:0] Analog COMP[3:0] must be terminated on the system board using precision (1%tolerance) resistors.
D[63:0]# Input/Output D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents.The data driver asserts DRDY# to indicate a valid data transfer.D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#.
Quad-Pumped Signal Groups::::::: ( Data Group DSTBN#/DSTBP#/ DINV#. D[15:0]#/ 0 /0; D[31:16]# /1/ 1; D[47:32]#/ 2 /2; D[63:48]# /3 /3. )
Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high.
DBR#Output DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.
DBSY# Input/Output DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents.
DEFER#Input DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents.
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DINV[3:0]# Input/Output DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle。
DINV[3:0]# Assignment To Data BusBus Signal /Data Bus Signals DINV[3]# /D[63:48]#；DINV[2]# /D[47:32]#；DINV[1]#/ D[31:16]#；DINV[0]#/ D[15:0]#。
DPSLP# Input DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State,DPSLP# must be deasserted. DPSLP# is driven by the ICH6-M chipset.
DPWR# Input DPWR# is a control signal from the Intel® 915PM/GM/GMS Express chipsets used to reduce power on Intel® Pentium® M data bus input buffers.
DRDY# Input/Output DRDY# (Data Ready) is asserted by the data driver on each data transfer,indicating valid data on the data bus. In a multi-common clock data transfer,DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents.
DSTBN[3:0]# Input/Output Data strobe used to latch in D[63:0]#. Signals/ Associated StrobeD[15:0]#, DINV[0]#/ DSTBN[0]#；D[31:16]#, DINV[1]#/ DSTBN[1]#；D[47:32]#, DINV[2]#/ DSTBN[2]#；
D[63:48]#, DINV[3]#/ DSTBN[3]#。
DSTBP[3:0]# Input/Output Data strobe used to latch in D[63:0]#. Signals/ Associated StrobeD[15:0]#, DINV[0]#/ DSTBP[0]#；D[31:16]#, DINV[1]#/ DSTBP[1]#；D[47:32]#, DINV[2]#/ DSTBP[2]#
D[63:48]#, DINV[3]#/ DSTBP[3]#。
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FERR#/PBE# Output FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*- type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the Intel ® Architecture Software Developer’s Manual and the Intel ® Processor Identification and CPUID Instruction application note.
GTLREF Input GTLREF determines the signal reference level for AGTL+ input pins. GTLREFshould be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0or logical1.
HIT#HITM#Input/Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
IERR# Output IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IGNNE#Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.
INIT# Input INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.INIT# must connect the appropriate pins of both FSB agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0] Input ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.
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LINT[1:0] Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APICBus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium Processor. Both signals are asynchronous.Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
LOCK# Input/Output LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock.
PRDY# Output Probe Ready signal used by debug tools to determine processor debug readiness.
PREQ# Input Probe Request signal used by debug tools to request debug operation of the processor.
PROCHOT# Output PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. See Chapter 5 for more details. This signal may require voltage translation on the motherboard.
PSI# Output Processor Power Status Indicator signal. This signal is asserted when the processor is in a lower state (Deep Sleep and Deeper Sleep). See Section 2.1.5 for more details.
PWRGOOD Input PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.
REQ[4:0]# Input/Output REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.
RESET# Input Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. There is a 55 ohm (nominal) on die pullup resistor on this signal.
RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents.
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RSVD Reserved/NoConnect These pins are RESERVED and must be left unconnected on the board.However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please refer to the platform design guide for more details.
SLP# Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state.
SMI# Input SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.
STPCLK# Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
TCK Input TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port).Please refer to the platform design guide for termination requirements and
implementation details.
TDI Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.Please refer to the platform design guide for termination requirements and implementation details.
TDO Output TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.Please refer to the platform design guide for termination requirements and implementation details.
TEST1,TEST2Input TEST1 and TEST2 must have a stuffing option of separate pull down resistors to VSS. Please refer to the platform design guide for more details.
THERMDA Other Thermal Diode Anode.
THERMDC Other Thermal Diode Cathode.
THERMTRIP# Output The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125 °C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. For termination requirements please refer to the platform design guide
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TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Please refer to the platform design guide for termination requirements and implementation details.
TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents.
TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Please refer to the platform design guide for termination requirements and implementation details.
VCC Input Processor core power supply.
VCCA Input VCCA provides isolated power for the internal processor core PLL’s. Pins previously named VCCA[3:1] pins are now reserved and should be left unconnected on the board. Refer to the platform design guide for complete implementation details.
VCCP Input Processor I/O Power Supply.
VCCQ[1:0] Input Quiet power supply for on die COMP circuitry. These pins should be connected to VCCP on the motherboard. However, these connections should enable addition of decoupling on the VCCQ lines if necessary.
VCCSENSE Output VCCSENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise. Please refer to the platform design guide for termination recommendations and more details.
VID[5:0] Output VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by Pentium M Processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID
pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 3-2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself.
VSSSENSE Output VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. Please refer to the platform design guide for termination recommendations and more details.
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发表于 2009-2-27 02:15:43
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