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12#
发表于 2008-10-29 12:29:23
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只看该作者
来自: 广东深圳 来自 广东深圳
ICH10 EDS描述如下:
Platform Reset: The Intel® ICH10 asserts PLTRST# to reset devices
on the platform (e.g., SIO, FWH, LAN, (G)MCH, TPM, etc.). The ICH10
asserts PLTRST# during power-up and when S/W initiates a hard reset
sequence through the Reset Control register (I/O Register CF9h). The
ICH10 drives PLTRST# inactive a minimum of 1 ms after both PWROK
and VRMPWRGD are driven high. The ICH10 drives PLTRST# active a
minimum of 1 ms when initiated through the Reset Control register
(I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.
附件是ICH10的几个时序供参考,没有专门真对cpurst#:
Intel® 4 Series Chipset Platform Sequencing:- ICH10 Sequencing Diagram
Intel® 4 Series Chipset Platform Sequencing:- GMCH Sequencing Diagram
Intel® 4 Series Chipset Platform Sequencing:- CPU VR Sequencing Diagram |
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