主板上的各种时钟是如何得来的

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译文在2#

What is a PLL?
A phase-locked loop (PLL) is an electronic circuit with a voltage- or current-driven oscillator that is constantly adjusted to match in phase (and thus locked on) the frequency of an input signal. PLLs are used for frequency control. They can be configured as frequency multipliers, dividers, demodulators, tracking generators or clock recovery circuits.

On a computer motherboard a PLL is used to generate several frequencies that are required for proper operation:

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Let's try to build our own PLL: What we want is a stable frequency that we can change on the fly.
A crystal oscillator would give us a stable frequency- but it's fixed and using several oscillators would be a waste of resources.
If we use a VCO (Voltage Controlled Oscillator) we get a freely changeable frequency but the frequency would change even at the slightest variation of voltage. If there was a way to combine the stability of the crystal oscillator with the flexibility of the VCO we would have the perfect solution for our problem.

What if we add a phase detector? A phase detector is a device that takes two signals. If both have the same phase and frequency the output is zero. If the signals are out-of-phase the output will be a DC voltage that is proportional to the phase difference between the two inputs.

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What does this do? The crystal generates a frequency of 10 MHz in our example. This frequency gets fed to the PD. The VCO output is zero right now so the PD output is high because the frequencies differ a lot. The PD output gets fed into the VCO and generates a frequency. This goes back to the PD and so on - eventually the VCO will lock onto the frequency of the crystal. And the output of the VCO will be 10 MHz. This is a basic PLL circuit.
Now you ask where's the flexibility? What we have right now is equivalent to a crystal oscillator!

Let's see.. We want an output of 20 Mhz for this example. What we do now is add a divide-by-two counter between the VCO output and the PD. This 'tricks' the PD into thinking our output frequency is only the half of what it really is- so it starts regulating the voltage to the VCO. Voila 20 MHz. If we used a programmable divider here we could change frequencies on the fly.

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Now we can multiply frequencies by integer values. But how can we multiply our frequency by fractional values or divide it?
For example we want 10 Mhz x 3.5 for an output of 35 Mhz. This is done by adding another pre-divider [whats the correct term here?] between the crystal and the PD. In our example we could use a pre-divider of 2 and a divider of 7. Our output would be 10 Mhz / 2 * 7 = 35 MHz.

This is our PLL in all its goodness:

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The added loop filter is not required for general understanding. It's here for completeness. The loop filter is designed to match the characteristics required by the application of the PLL. For example, it determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate. The narrower the loop filter bandwidth the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range.

[ 本帖最后由 张先生 于 2007-6-22 18:53 编辑 ]

会员3847

锁相环（PLL）是一个具有电压或电流驱动振荡器的电子电路，它不断调整相位匹配（并这样锁定）一个输入信号的频率。PLL作为频率控制器使用，它们可以构造成倍频器，分频器，解调器，跟踪信号发生器或者时钟恢复电路。

在计算机主板上PLL用于产生工作所要求的一些频率：

                               
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让我们建造一个自己的PLL:我们需要的是一个我们可以飞快改变的稳定频率。
晶体振荡器可以给我们提供稳定的频率--但是它是固定的，使用多个振荡器将是资源的浪费。
如果我们用一个VCO（电压控制振荡器），我们可以得到一个可以自由改变的频率，但是这个频率甚至只要有最轻微的电压变化就会改变。
如果我们找到一种方法用可变的VCO来组合稳定的晶体振荡器，可以成为解决我们的问题优秀解决方案。

如果我们加一个鉴相位会如何？鉴相器是一个有两个输入信号的器件，如果二者具有相同的相位和频率则输出为零。如果信号的相位有差别就会输出一个DC（直流）电压，这个电压正比于两个输入间的相位差。

                               
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这有什么用呢？在我们的例子里晶体产生10MHz频率，这个频率馈送到PD（鉴相器），VCO的输出为零，所以PD的输出是高的，因为频率差得太大。PD的输出馈送到VCO，VCO产生一个频率，这又送回到PD，过程不断进行，最终VCO将锁定到晶体的频率上，VCO的输出也将是10MHz。这是一个基本的PLL电路。
现在你要问可变性在那里？现在我们所得到的是一个等价于晶体振荡器的东西。

让我们来看，作为这个例子，我们想要一个输出20MHz的信号，我们要做的是在VCO输出和PD之间添加一个二分频计数器，这个诀窍让PD认为是实际频率的一半，所以它开始调整VCO电压使它达到20MHz。如果我们用一个可编程分频器，我们就可以改变频率于瞬间。

                               
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现在我们可以倍增整数频率，但是我们如何以分数倍增频率，或者分频呢？
以我们需要10MHz X 3.5，即35MHz输出。这可以在晶体和PD之间再加一个预分频[这里的正确术语是什么？]。在我们的例子中，我们可以预分频2和分频7，输出将是10Mhz/2*7 = 35MHz。

这是我们得到的不错的PLL。

                               
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加进去的回路滤波器作为一般的了解是不一定需要的，放在这里是为了完整。回路滤波器被设计成PLL应用所需要的特性。例如它决定信号变化多快仍然可以维持锁定。这就是最大回转率。滤波器的带宽越窄，得到的相位差越小，其代价为响应变慢俘获范围变小。

[ 本帖最后由 张先生 于 2007-6-22 18:36 编辑 ]

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張先生太強了，這麼專業的東西，翻譯得這麼准，可見功底了得。