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4#
·¢±íÓÚ 2011-4-20 22:56:20
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ADP3168Ó¦¸ÃÄÜ´úADP3181°É?´Ó×ÊÁÏÉÏ¿´Ö÷Òª¾ÍÊǵÚ6½ÅÓÐÇø±ðÁË.
ADP3168:
1 to 6 VID4 to VID0, VID5 :Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing
a Logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation
voltage from 0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3168 going into
a no CPU mode, shutting off its PWM outputs.
ADP3181:
1 to 5 VID4 to VID0 : Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a Logic 1
if left open. When in normal operation mode, the DAC output programs the FB regulation voltage based
on the condition of the CPUID pin (see Table 4 and Table 5). Leaving VID4 through VID0 open results in
ADP3181 going into a no CPU mode, shutting off its PWM outputs.
6 CPUID: CPU DAC Code Selection Input. When this pin is pulled > 4.25 V, the internal DAC reads its inputs based
on the VRM 9 VID table (see Table 4). When this pin is <4 V, the DAC reads its inputs based on the VRD
10 VID table (see Table 5) and treats CPUID as the VID5 input. (ADP3181JRQ, VRD10 only)
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