Intel chipset 6 series _ deep sleep state.

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Intel has introduced another sleep state towards Intel chipset 6 series known as deep sleep state.

Now our board with Intel chipset 6 has four wells,
1. RTC well.
2. Deep sleep well.
3. Suspend well.

And  
4. Core well.
Deep sleep well is brought to save more power. Because EC release S5_ON, when deep sleep well meet its conditions and communicate to EC for further proceedings.

How does it work?
PCH got another section which is known as DSW. As it receives the power from the same source RTC VCC and DSW power good (or designed by
vender .) 1. PCH releases SUSWARN# signal for the EC.
2. EC acknowledges back through SUS_ACK#. That I am ready to release the s5_on signal.  
3. Then PCH sends the signal SLP_SUS# to EC controller.

These all # signals must be high while turning on the board.

And EC releases the S5_ON signal for The further proceedings.