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Nios II 嵌入式系统驱动设
最近一直在做SOPC自定义元件的设计及其驱动的编写，今天先分享一些关于自定义元件端口设置的内容。
在版本8.0中，SOPC Builder已经集成了七十多个IP，用户可以非常方便的应用这些元件，不过在实际应用的时候，有些元件并没有包含在SOPC中，需要用户自己编写元件代码，并集成进SOPC Builder里面，自定义元件的集成过程其实就是将元件通过Avalon总线兼容的端口挂载到Avalon总线上，因此最重要的一步就是设置元件的端口，使其能挂载到Avalon总线上。
在7.2版本之后，Quartus II在自定义元件端口设置方面做了很大的修改，下面是变更的内容。
Table 1. Current Avalon Interfaces Supported by the Component Editor
Interface Type
Default NameDescriptionNew Interface in v7.2
Master
avalon_master or m0Defines an Avalon master port interface.
-
Slave
avalon_slave or s0Defines an Avalon slave port interface.
-
Tri-State Slave
avalon_tristate_slaveDefines an Avalon tri-state port interface.
-
Clock Input
clock or clock_sinkDefines a clock and reset input interface for a component.
Y
Clock Output
clock_sourceDefines a clock and reset output interface for components that generate clocks for SOPC Builder systems.
Y
Conduit Output or Input
conduit_start or conduit_endUsed for exporting signals to the top level of SOPC Builder systems. Conduit output and input interfaces are identical and imply no signal direction for the conduit interface. Conduits can contain input, output, and bidirectional signals.
Y
Interrupt Sender
interrupt_senderDefines an interrupt output signal and the Avalon slave interface that is associated with generating the interrupt signal.
Y
Interrupt Receiver
interrupt_receiverDefines an interrupt input signal and the Avalon master interface that is associated with receiving interrupt signals.
Y
Streaming Source
avalon_streaming_sourceDefines an Avalon streaming source port interface.
Y
Streaming Sink
avalon_streaming_sinkDefines an Avalon streaming sink port interface.
Y
我们可以发现除了已有的Master，slave以及tri-state slave以外，还新增了流处理端口，中断收发端口，时钟及输出端口。因为在7.2版本以后，除了Avalom-MM总线外，SOPC又新增了Avalon-ST总线，因此端口也相应的增加了。
下面列出在7.2版本后主端口和从端口所需的端口信号，表中还列出了和以前版本的端口比较。
Table 1. Avalon-MM Slave with Global Clock, Reset, Interrupt Output, and Export Signals
Signal Type
Directionv7.1 and Earlier Interfacev7.2 and Later Interface
clk
InputGlobal
Clock Input (1)
reset
Input
Global
Clock Input (1)
address
Input
Avalon Slave
Avalon Slave
read
Input
Avalon Slave
Avalon Slave
readdata
OutputAvalon SlaveAvalon Slave
write
Input
Avalon Slave
Avalon Slave
writedata
InputAvalon SlaveAvalon Slave
waitrequest
OutputAvalon SlaveAvalon Slave
irq
OutputAvalon SlaveInterrupt Sender
my_export_signals
Input, Output, or BidirGlobalConduit
Table 2. Avalon-MM Multi-Port Slave with Global Clock, Reset, and Export Signals
Signal Type
Directionv7.1 and Earlier Interfacev7.2 and Later Interface
clk
InputGlobalClock Input (1)
reset
InputGlobalClock Input (1)
s1_address
InputAvalon S1 SlaveAvalon S1 Slave
s1_read
InputAvalon S1 SlaveAvalon S1 Slave
s1_readdata
OutputAvalon S1 SlaveAvalon S1 Slave
s1_write
InputAvalon S1 SlaveAvalon S1 Slave
s1_writedata
InputAvalon S1 SlaveAvalon S1 Slave
s1_waitrequest
OutputAvalon S1 SlaveAvalon S1 Slave
s1_export_signals
Input, Output, or BidirAvalon S1 SlaveS1 Conduit
s2_address
InputAvalon S2 SlaveAvalon S2 Slave
s2_read
InputAvalon S2 SlaveAvalon S2 Slave
s2_readdata
OutputAvalon S2 SlaveAvalon S2 Slave
s2_write
InputAvalon S2 SlaveAvalon S2 Slave
s2_writedata
InputAvalon S2 SlaveAvalon S2 Slave
s2_waitrequest
OutputAvalon S2 SlaveAvalon S2 Slave
s2_export_signals
Input, Output, or BidirAvalon S2 SlaveS2 Conduit
Table 3. Avalon-MM Master with Global Clock, Reset, Interrupt Input, and Export Signals
Signal Type
Directionv7.1 and Earlier Interfacev7.2 and Later Interface
clk
InputGlobalClock Input (1)
reset
InputGlobalClock Input (1)
address
OutputAvalon MasterAvalon Master
read
OutputAvalon MasterAvalon Master
readdata
InputAvalon MasterAvalon Master
write
OutputAvalon MasterAvalon Master
writedata
OutputAvalon MasterAvalon Master
waitrequest
InputAvalon MasterAvalon Master
irq
InputAvalon MasterInterrupt Receiver
my_export_signals
Input, Output, or BidirGlobalConduit
Table 4. Avalon-MM Multi-Port Slave with Interface-Specific Clocks and Export Signals
Signal Type
Directionv7.1 and Earlier Interfacev7.2 and Later Interface
s1_clk
InputAvalon S1 SlaveS1 Clock Input (1)
s1_reset
InputAvalon S1 SlaveS1 Clock Input (1)
s1_address
InputAvalon S1 SlaveAvalon S1 Slave
s1_read
InputAvalon S1 SlaveAvalon S1 Slave
s1_readdata
OutputAvalon S1 SlaveAvalon S1 Slave
s1_write
InputAvalon S1 SlaveAvalon S1 Slave
s1_writedata
InputAvalon S1 SlaveAvalon S1 Slave
s1_waitrequest
OutputAvalon S1 SlaveAvalon S1 Slave
s1_export_signals
Input, Output, or BidirAvalon S1 SlaveS1 Conduit
s2_clk
InputAvalon S2 SlaveS2 Clock Input (1)
s2_reset
InputAvalon S2 SlaveS2 Clock Input (1)
s2_address
InputAvalon S2 SlaveAvalon S2 Slave
s2_read
InputAvalon S2 SlaveAvalon S2 Slave
s2_readdata
OutputAvalon S2 SlaveAvalon S2 Slave
s2_write
InputAvalon S2 SlaveAvalon S2 Slave
s2_writedata
InputAvalon S2 SlaveAvalon S2 Slave
s2_waitrequest
OutputAvalon S2 SlaveAvalon S2 Slave
s2_export_signals
Input, Output, or BidirAvalon S2 SlaveS2 Conduit
Table 5. Avalon-MM Multi-Port Master and Slave with Interface-Specific Clocks
Signal Type
Directionv7.1 and Earlier Interfacev7.2 and Later Interface
slave_clk
InputAvalon SlaveSlave Clock Input (1)
save_reset
InputAvalon SlaveSlave Clock Input (1)
slave_address
InputAvalon SlaveAvalon Slave
slave_read
InputAvalon SlaveAvalon Slave
slave_readdata
OutputAvalon SlaveAvalon Slave
slave_write
InputAvalon SlaveAvalon Slave
slave_writedata
InputAvalon SlaveAvalon Slave
slave_waitrequest
OutputAvalon SlaveAvalon Slave
master_clk
InputAvalon MasterMaster Clock Input (1)
master_reset
InputAvalon MasterMaster Clock Input (1)
master_address
OutputAvalon MasterAvalon Master
master_read
OutputAvalon MasterAvalon Master
master_readdata
InputAvalon MasterAvalon Master
master_write
OutputAvalon MasterAvalon Master
master_writedata
OutputAvalon MasterAvalon Master
master_waitrequest
InputAvalon MasterAvalon Master
确定了需要哪些端口后，需要编写元件代码（Verilog或VHDL），在端口命名中，Altera推荐用如下命名方式，以便在导入component editor之后能自动识别成相应的interface type。
__[_n]
interface type如下表所示：
比如下面的端口定义：
module my_slave_irq_component (
// Signals for Avalon-MM slave port “s1” with irq
csi_clockreset_clk; //clockreset clock interface
csi_clockreset_reset_n;//clockreset clock interface
avs_s1_address;//s1 slave interface
avs_s1_read; //s1 slave interface
avs_s1_write; //s1 slave interface
avs_s1_writedata; //s1 slave interface
avs_s1_readdata; //s1 slave interface
ins_irq0_irq; //irq0 interrupt sender interface
);
input csi_clockreset_clk;
input csi_clockreset_reset_n;
input [7:0]avs_s1_address;
input avs_s1_read;
input avs_s1_write;
input [31:0]avs_s1_writedata;
output [31:0]avs_s1_readdata;
output ins_irq0_irq;
/* Insert your logic here */
endmodule
当元件设置好端口，并编写完相应的Verilog或VHDL代码之后，并可以通过SOPC Builder中的Component editor集成进SOPC Builder中，用户并可以非常方便的调用。关于这部分内容请参考SOPC自定义元件的添加及运行。
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狗仔卡
发表于 2016-3-5 10:38:00
支持！
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