④⑦⑤0G的机器 HM65 不读内存 求助

会员590038

因等级 权限问题 没有办法上传图纸  
版号：JE40 HR MB 10267-4
机器 进水区域  EC 背面和桥背面
一量 桥 短路 直接不说啥了 换的新桥 HM65 无铅
冷却后 安装CPU  内存 风扇  电流跑 0.85A  风扇狂转
CPU 复位1.05V AY11的位置
测无集显供电  测CPU 电压 已出  1.1V
测独立显卡供电 已出 时钟 已出 正XUAN波  测到复位的时候    无
于是 测了下 内存 复位 1.57V  测下 200  202  有电压 3.4V  无波形
内存的 主供电和副供电 都已经出来  
测桥供电 和时钟 都正常
lpc 对地 490  电压 3.4V 无波
求哥哥们 知道这个HM65 平台的 不跑码的维修思路！

PCH_SMBCLK 和data  对地 663  有电压3.4V 无波形
PM_DRAM_PWRGOOD 3.4V
VDDPWRGOOD 1.5V
BUF_CPU_RST# 1.13V  CPU复位
H_A20GATE 3.42  
H_CPUPWRGD 1.05V
LPC总线 有电压 3.42V 对地 493  4根线对地 一样  测无波形
仅仅测CPU 时钟没有测到 一会儿 测过后补上数据

会员885979

等待高人解答学习一下

会员912911

换新桥最好刷下BIOS

会员590038

汪洋.. 发表于 2014-7-21 23:38
换新桥最好刷下BIOS

在回复刷BIOS和换桥 罚你站墙角 并植球 100次 全是0.3的球

会员590038

框架图  希望有修好之后 多多测试 留下实验数据

会员590038

H_SNB_IVB#（DF_TVS）
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST# deasserts.

THRMTRIP# :是CPU温度检测信号
Thermal Trip: When low, this signal indicates that a thermal trip
from the processor occurred, and the PCH will immediately transition
to a S5 state. The PCH will not wait for the processor stop grant cycle
since the processor has overheated.

PROCPWRGD:CPU 电源好信号
This signal is connected to the processor’s UNCOREPWRGOOD input to indicate when
the processor power is valid.

PMSYNCH:电源管理同步
Power Management Sync: Provides state information from the PCH
to the processor

DRAMPWROK ：DRAM Power OK， This signal should connect to the processor’s
SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM
power is stable.
This pin requires an external pull-up

PLTRST#平台复位
Platform Reset: The PCH asserts PLTRST# to reset devices on the
platform (such as SIO, FWH, LAN, processor, etc.). The PCH asserts
PLTRST# during power-up and when S/W initiates a hard reset
sequence through the Reset Control register (I/O Register CF9h). The
PCH drives PLTRST# active a minimum of 1 ms when initiated through
the Reset Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.

CLKOUT_DMI_N,CLKOUT_DMI_P(CLK_CPU_BCLKP，CLK_CPU_BCLKN，)
100 MHz PCIe* Gen2.0 differential output to the
processor for DMI/BCLK.

CLKOUT_DP_P, CLKOUT_DP_N (CLK_DPLL_SSCLKP，CLK_DPLL_SSCLKN)
120 MHz Differential output for DisplayPort reference

sys_reset#：（XDP_DBRST#）,System Reset: This pin forces an internal reset after being
debounced. The PCH will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ±2 ms for the SMBus to idle before
forcing a reset on the system.

SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the
PCH attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go
idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately;
otherwise, the counter starts. If at any point during the count the SMBus goes idle the
reset occurs. If, however, the counter expires and the SMBus is still active, a reset is
forced upon the system even though activity is still occurring.
Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the
SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET#
has been detected inactive after the debounce logic, and the system is back to a full S0
state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then
SYS_RESET# will result in a full power cycle reset.
SYS_RESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets and avoids improperly reporting power failures.

会员422487

楼主你留下这么多信号有没有修好啊！我的跟你一样的故障，南桥显卡BIOS都刷完了。。

会员16171

CPU未能读取BIOS程序，或者程序有问题，

会员884966

等待答案 出来

会员892905

楼主把你的HM65的数据手册，传上来给大家看看，我现在非常需要HM65的数据手册

会员892905

我的邮箱是591717330@QQ.COM

会员623900

楼主搞定没有，我也有台G470也是跟你情况差不多！

会员626

yjinxing2020 发表于 2014-9-14 17:53
楼主把你的HM65的数据手册，传上来给大家看看，我现在非常需要HM65的数据手册

去GOOGLE搜一下.或者去INTEL的官网下载